The present invention is related to systems and methods for decoding information, and more particularly to systems and methods for LDPC decoding using the sum product.
A number of encoding/decoding schemes have been developed to meet the needs for, among other things, data storage and data transmission. As one example, low-density parity-check (LDPC) codes have been developed that provide excellent error correcting performance using a highly parallelized decoding algorithm. Various implementations of an LDPC decoder implement a sum product algorithm.
Turning to FIG. 1, an exemplary prior art check-to-bit circuit (i.e., a row update circuit) 100 is depicted. In this example, the parity check matrix has columns of weight four and rows of weight thirty-six, and includes a total of 18,432 nonzero entries. The parity check information is also commonly represented in a bi-partite graph as five hundred, twelve (512) check nodes and four thousand, six hundred and eight (4608) bit nodes. Of note, the architecture includes two distinct look up tables 110, 112 and two distinct FIFO memories 120, 122 that are used to implement a sum product algorithm. In particular, the architecture of check-to-bit circuit 100 uses both look up tables 110, 112 at the same time during a row update. Such an architecture provides reasonable decode results, however, it is expensive in terms of circuitry and die area.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for decoding information.